TIM-8121 v1

Espinosa-Jimenez, L.M., & Opoku-Agyeman, M. (2018). A study of techniques to increase instruction level parallelisms. Computer Science and Intelligent Control, 1–5.

This resource explores improvement techniques for instruction-level parallelisms.

Rajper, A., Talpur, S., Laghari, N.-U.-Z., & Rajper, N. J. (2017). Analysis of performance of instruction pipeline with transactional slice mechanism in CMP[Conference presentation]. 2017 UKSim-AMSS 19th International Conference on Computer Modelling & Simulation (UKSim), 209–214.

This resource offers a detailed analysis of an instruction pipeline.

Vladimir Kiriansky, Haoran Xu, Martin Rinard, & Saman Amarasinghe. (2018). Cimple: Instruction and memory level parallelism : A DSL for uncovering ILP and MLP. Parallel Architectures and Compilation Techniques, 1–16.

This resource presents IMLP (Instruction and Memory Level Parallelism) task programming model.

Rajper, A., Talpur, S., Laghari, N.-U.-Z., & Rajper, N. J. (2017). Analysis of performance of instruction pipeline with transactional slice mechanism in CMP [Conference presentation]. 2017 UKSim-AMSS 19th International Conference on Computer Modelling & Simulation (UKSim), 209–214.

This resource offers a detailed analysis of an instruction pipeline.

Hashemi, S. H., Ajirlou, A. F., Soltani, M., & Navabi, Z. (2016). Early prediction of timing critical instructions in pipeline processor [Conference presentation]. 2016 15th Biennial Baltic Electronics Conference (BEC), 95–98.

This resource explains the inner working of a processor and how it handles an instruction pipeline.

Omran, S. S., & Jumma, L. F. (2017). Design of multithreading SHA-1 & SHA-2 MIPS processor using FPGA [Conference presentation]. 2017 8th International Conference on Information Technology (ICIT), 632–637.

This resource demonstrates how multithreading works in detail.